Mentor Graphics Application Engineer - Digital Functional Verification - 5941 in Herzliya Pituah, Israel
Application Engineer - Digital Functional Verification - 5941
Company: Mentor Graphics
Job Title: Application Engineer - Digital Functional Verification -5941
Job Location: Israel – Herzliya
Job Category: Applications Engineering
As European Application Engineer for digital functional verification you play a critical role to the success of Mentor Graphics. You will be part of an Application Engineering team managed by the European Technical Director for Digital Design and Verification Solutions.
You are expected to leverage your expertise in Functional Verification to help our customers improve their verification capabilities, identifying and providing solutions to overcome their verification challenges and delivering expert assistance in the deployment of Mentor tools, technology and services.
The successful candidate will:
• Drive business for Mentor Graphics using hands-on technical expertise. This requires working directly with customers as a part of the sales team.
• Provide customer verification methodology guidance, verification tools training, and verification problem resolution.
• Align with Sales to exceed quota as they proactively manage customer accounts to achieve business success. Sales support roles include product demonstrations, evaluations and competitive benchmarking.
• Work with customers to solve complex technical challenges in multiple disciplines of functional verification including Assertion Based Verification, Coverage Driven Verification, Formal Verification, Low Power Verification, and Verification Management.
• Support existing customers with the use of Mentor verification tools, ensuring they are kept up to date with new capabilities and that the tools deliver capabilities that meet their needs.
• Provide technical feedback to Mentor product development teams relating to critical issues and recommended product enhancements.
• Manage multiple customer issues concurrently, working with design & verification engineers, as well as first or second level managers.
• Be expected to take advantage of opportunities provided to improve technical and job related skills; such as developing additional product breadth and business skills.
• Education: MSEE (or equivalent) required with 3+ years experience or BSEE (or equivalent) with 5+ years experience in the area of functional verification.
• Experience should include
o Chip/ASIC/FPGA design or verification experience - knowledge ofSystemVerilog/Verilog/VHDL language, RTL, behavioral coding and general ASIC debug.
o In-depth technical knowledge of asynchronous clock domain crossing verification.
o Detailed knowledge of static and formal verification technology & techniques.
o Experience with use of assertion based verification using SVA, PSL or similar.
o Expert level usage of at least one major verification platform (Questa, Incisive, VCS, Specman).
o Working knowledge of dynamic verification methodologies (UVM/OVM,VMM or eRM) and verification languages (SystemVerilog, SystemC, e, Vera).
o Experience with Linux and Windows environments including scripting languages.
• General knowledge of Functional Verification disciplines including Assertion Based Verification, Formal Verification, Low-Power Verification, Verification Management and Verification Methodology with demonstrated expertise in at least two of these areas.
• Experience with Mentor Functional Verification products - advantage.
• Excellent verbal and written presentation and communication skills are required.
• The ability to thrive in a dynamic environment including the ability to multiplex many issues, establish and meet priorities, while maintaining a helpful/caring attitude towards fellow workers, and customers.
• A desire to help customers exploit new technologies is essential for success in the position.
• English mandatory.
• Willingness to travel (domestically and internationally).