Marvell Engineering - Hardware - Design Verification in Petach, Israel
The engineer will take ownership over a unit or several units. He will do unit level design and verification and will plan and execute the verification. He will also participate in the cluster level verification. The engineer will work with architects to understand and influence the unit architecture, plan and implement design changes in Verilog or SV, plan and implement verification environment in UVM, and execute the verification plan until quality criteria is met.
- #LI-BA1 *
• Electrical engineering B.Sc graduate • Design RTL experience in Verilog or SV • Verification experience in SV, UVM, perl, • Knowledge in programming • Good learning skills • Problems solving skill • Ability to be a part of a team, working in cooperation
Job: *Engineering - Hardware
Title: Engineering - Hardware - Design Verification
Requisition ID: 171299