Marvell Engineering - Hardware - Physical Design in Petach, Israel
Be part of chip back end team Ability to run Macros from RTL to GDS using common Synopsys and Cadence tools , define and debug timing constrain, Macro floor planning and timing closure Independent work capabilities , self-managed and multi-tasking
- #LI-BA1 *
Education: • B.Sc. in Electrical Engineering Requirements: • 5 years in Backend design in advanced technologies. Synopsys/Cadence flows – advantage • Deep knowledge in Backend flow RTL-GDSII, physical synthesis, Floorplan, place & route, CTS, static timing, power analysis & timing driven. • HandsOn experience in macro level flows including STA capabilities and LO Verification. • Extensive background in low power design and high frequency design methodologies. • RTL Design background – advantage. • Advanced process experience (28nm/16nm) – advantage.
Job: *Engineering - Hardware
Title: Engineering - Hardware - Physical Design
Requisition ID: 170356